Hierarchical art was used to solve the mixed mode placement for three dimensional(3-D)integrated circuit design.The 3-D placement flow stream includes hierarchical clustering,hierarchical 3-D floorplanning, vertical via mapping,and recursive two dimensional(2-D)global/detailed placement phases.With state-of-the-art clustering and de-clustering phases,the design complexity was reduced to enhance the placement algorithm efficiency and capacity.The 3-D floorplanning phase solved the layer assignment problem and controlled the number of vertical vias.The vertical via mapping transformed the 3-D placement problem to a set of 2-D placement sub-problems,which not only simplifies the original 3-D placement problem, but also generates the vertical via assignment solution for the routing phase.The design optimizes both the wire length and the thermal load in the floorplan and placement phases to improve the performance and reliability of 3-D integrate circuits.Experiments on IBM benchmarks show that the total wire length is reduced from 15%to 35%relative to 2-D placement with two to four stacked layers,with the number of vertical vias minimized to satisfy a pre-defined upper bound constraint.The maximum temperature is reduced by 16% with two-stage optimization on four stacked layers.
With its advantages in wirelength reduction and routing exibility compared with conventional Manhattan routing, X architecture has been proposed and applied to modern IC design. As a critical part in high-performance integrated circuits, clock network design meets great challenges due to feature size decrease and clock frequency increase. In order to eliminate the delay and attenuation of clock signal introduced by the vias, and to make it more tolerant to process variations, in this paper, we propose an algorithm of a single layer zero skew clock routing in X architecture (called Planar-CRX). Our PlanarCRX method integrates the extended deferred-merge embedding algorithm (DME-X, which extends the DME algorithm to X architecture) with modified Ohtsuki’s line-search algorithm to minimize the total wirelength and the bends. Compared with planar clock routing in the Manhattan plane, our method achieves a reduction of 6.81% in total wirelength on average and gets the resultant clock tree with fewer bends. Experimental results also indicate that our solution can be comparable with previous non-planar zero skew clock routing algorithm.
