传统的Gm-C滤波器OTA输入晶体管大多工作在饱和区,存在输入动态范围较小和跨导值较大等不足,难以满足生物医学电信号处理滤波器所要求的超低截止频率、低功耗与大输入动态范围等要求,采用将输入晶体管钳位到线性工作区的方法,设计了跨导线性可调的OTA以提高滤波器能够处理的信号幅度。并应用该OTA综合了一种五阶Gm-C超低频低通滤波器。仿真结果表明,该滤波器在1.8 V电源,800 m Vpp输入条件下实现了283 Hz的超低低通角频率,-6.4 d B的带内增益,51 d B的三次谐波失真,功耗仅为22μW,适用于可穿戴式生物医学电信号读取电路。
This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5μW with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.
A three-stage differential voltage-controlled ring oscillator is presented for wide-tuning and low-phase noise requirement of clock and data recovery circuit in ultra wideband（UWB） wireless body area network. To improve the performance of phase noise of delay cell with coarse and fine frequency tuning, injection locked technology together with pseudo differential architecture are adopted. In addition, a multiloop is employed for frequency boosting. Two RVCOs, the standard RVCO without the IL block and the proposed IL RVCO, were fabricated in SMIC 0.18 m 1P6 M Salicide CMOS process. The proposed IL RVCO exhibits a measured phase noise of –112.37 d Bc/Hz at 1 MHz offset from the center frequency of 1 GHz, while dissipating a current of 8 m A excluding the buffer from a 1.8-V supply voltage. It shows a 16.07 d B phase noise improvement at 1 MHz offset compared to the standard topology.
An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio （PSRR） and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/℃ in a range from 25 to 100 ℃. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3,3 V, and PSRR is -49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm2. The circuit can be used as an elementary circuit block for power-aware ASICs.
A fifth order operational transconductance amplifier-C （OTA-C） Butterworth type low-pass filter with highly linear range and less passband attenuation is presented for wearable bio-telemetry monitoring applications in a UWB wireless body area network. The source degeneration structure applied in typical small transconduc- tance circuit is improved to provide a highly linear range for the OTA-C filter. Moreover, to reduce the passband attenuation of the filter, a cascode structure is employed as the output stage of the OTA. The OTA-based circuit is operated in weak inversion due to strict power limitation in the biomedical chip. The filter is fabricated in a SMIC 0.18-μm CMOS process. The measured results for the filter have shown a passband gain of -6.2 dB, while the -3-dB frequency is around 276 Hz. For the 0.8 Vpp sinusoidal input at 100 Hz, a total harmonic distortion （THD） of-56.8 dB is obtained. An electrocardiogram signal with noise interference is fed into this chip to validate the function of the designed filter.
