A new low leakage 3×VDD-tolerant electrostatic discharge(ESD)detection circuit using only low-voltage device without deep N-well is proposed in a standard 90-nm 1.2-V CMOS process.Stacked-transistors technique is adopted to sustain high-voltage stress and reduce leakage current.No NMOSFET operates in high voltage range and it is unnecessary to use any deep N-well.The proposed detection circuit can generate a 38 mA current to turn on the substrate triggered silicon-controlled rectifier(STSCR)under the ESD stress.Under normal operating conditions,all the devices are free from over-stress voltage threat.The leakage current is 88 nA under 3×VDD bias at 25°C.The simulation result shows the circuit can be successfully used for 3×VDD-tolerant I/O buffer.
An electrostatic discharge(ESD) detection circuit with a modified RC network for a 90-nm process clamp circuit is proposed.The leakage current is reduced to 4.6 nA at 25℃.Under the ESD event,it injects a 38.7 mA trigger current into the P-substrate to trigger SCR,and SCR can be turned on the discharge of the ESD energy.The capacitor area used is only 4.2μm^2.The simulation result shows that the proposed circuit can save power consumption and layout area when achieving the same trigger efficiency,compared with the previous circuits.
