This paper presents a 10Gb/s high-speed equalizer as the front-end of a receiver for backplane communication.The equalizer combines an analog equalizer and a two-tap decision-feedback equalizer in a half-rate structure to reduce the inter-symbol-interference(ISI) of the communication channel.By employing inductive peaking technique for the high-frequency boost circuit,the bandwidth and the boost of the analog equalizer are improved.The decision-feedback equalizer optimizes the size of the CML-based circuit such as D flip-flops(DFF) and multiplex(MUX),shortening the feedback path delay and speeding up the operation considerably.Designed in the 0.18μm CMOS technology,the equalizer delivers 10Gb/s data over 18-in FR4 trace with 28-dB loss while drawing27-mW from a 1.8-V supply.The overall chip area including pads is 0.6×0.7mm^2.
A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET(IMOS) varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27–32.5 GHz, exhibiting a frequency tuning range(FTR) of 18.4%and a phase noise of –101.38 dBc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of –185dBc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 m A DC current.
A CMOS low-noise amplifier(LNA) operating at 31.7 GHz with a low input return loss(S_(11)) and high linearity is proposed.The wideband input matching was achieved by employing a simple LC compounded network to generate more than one S_(11) dip below -10 dB level.The principle of the matching circuit is analyzed and the critical factors with significant effect on the input impedance(Z_(in)) are determined.The relationship between the input impedance and the load configuration is explored in depth,which is seldom concentrated upon previously. In addition,the noise of the input stage is modeled using a cascading matrix instead of conventional noise theory. In this way Z_(in) and the noise figure can be calculated using one uniform formula.The linearity analysis is also performed in this paper.Finally,an LNA was designed for demonstration purposes.The measurement results show that the proposed LNA achieves a maximum power gain of 9.7 dB and an input return loss of < -10 dB from 29 GHz to an elevated frequency limited by the measuring range.The measured input-referred compression point and the third order inter-modulation point are -7.8 and 5.8 dBm,respectively.The LNA is fabricated in a 90-nm RF CMOS process and occupies an area of 755×670μm^2 including pads.The whole circuit dissipates a DC power of 24 mW from one 1.3-V supply.
Two essential blocks for the PLLs based on CP, a phase-frequency detector(PFD) and an improved current steering charge-pump(CP), are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from –354° to 354° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage,swinging from 0.2 to 1.1 V, and the power consumption is 1.3 m W under a 1.2-V supply.
A dual-band, wide tuning range voltage-controlled oscillator that uses transformer-based fourth-order(LC) resonator with a compact common-centric layout is presented. Compared with the traditional wide band(VCO), it can double frequency tuning range without degrading phase noise performance. The relationship between the coupling coefficient of the transformer, selection of frequency bands, and the quality factor at each band is investigated. The transformer used in the resonator is a circular asymmetric concentric topology. Compared with conventional octagon spirals, the proposed circular asymmetric concentric transformer results in a higher qualityfactor, and hence a lower oscillator phase noise. The VCO is designed and fabricated in a 0.18- m CMOS technology and has 75% wide tuning range of 3.16–7.01 GHz. Depending on the oscillation frequency, the VCO current consumption is adjusted from 4.9 to 6.3 m A. The measured phase noises at 1 MHz offset from carrier frequencies of 3.1, 4.5, 5.1, and 6.6 GHz are –122.5, –113.3, –110.1, and –116.8 d Bc/Hz, respectively. The chip area, including the pads, is 1.20.62 mm2 and the supply voltage is 1.8 V.
This paper presents a word alignment circuit for high speed SerDes system.By using pipeline structure and circuit optimization techniques,the speed of the aligner is increased,and its performance is improved further through adopting the full custom design method.The proposed word aligner has fabricated in 0.18μm CMOS technology with total area of 1.075 ×0.775mm^2￣ including I/O pad.Measurement results show that this circuit achieves the maximum data rate of 14.5Gb/s,while consuming a total power of 34.9mW from a 1.8V supply.
