A novel voltage-withstand substrate with high-K（HK, k 〉 3.9, k is the relative permittivity） dielectric and low specific on-resistance（Ron,sp） bulk-silicon, high-voltage LDMOS（HKLR LDMOS）is proposed in this paper. The high-K dielectric and highly doped interface N＋-layer are made in bulk silicon to reduce the surface field drift region. The high-K dielectric can fully assist in depleting the drift region to increase the drift doping concentration（Nd） and reshape the electric field distribution. The highly doped N＋-layer under the high-K dielectric acts as a low resistance path to reduce the Ron,sp. The new device with the high breakdown voltage（BV）, the low Ron,sp, and the excellent figure of merit（FOM = BV^2/Ron,sp） is obtained. The BV of HKLR LDMOS is 534 V, Ron,sp is 70.6 m？·cm^2, and FOM is 4.039 MW·cm^（-2）.
A new SOl self-balance （SB） super-junction （S J） pLDMOS with a self-adaptive charge （SAC） layer and its physical model are presented. The SB is an effective way to realize charges balance （CB）. The substrate-assisted depletion （SAD） effect of the lateral SJ is eliminated by the self-adaptive inversion electrons provided by the SAC. At the same time, high concentration dynamic self-adaptive electrons effectively enhance the electric field （EI） of the dielectric buried layer and increase breakdown voltage （BV）. E1 = 600 V/μm and BV =- 237 V are obtained by 3D simulation on a 0.375-μm-thick dielectric layer and a 2.5-μm-thick top silicon layer. The optimized structure realizes the specific on resistance （Ron,sp） of 0.01319Ω·cm2, FOM （FOM = BV2/R p） of 4.26 MW/cm2 under a 11 μm length （Ld） drift region.
A novel silicon-on-insulator(SOI)high-voltage device of super-junction(SJ)lateral-double-diffused metal-oxide-semiconductor transistors(LDMOSTs)with T-dual dielectric buried layers(T-DBLs)is presented.The T-DBLs are formed by the first T-shaped dielectric layer and the second dielectric layer.A lot of holes are accumulated on the top interface of the second dielectric layer,which compensates for the charge imbalance of the surface N and P pillars,thus the substrate-assisted depletion(SAD)effect is eliminated in the new device.The electric field of the second dielectric buried layer,EI2,is enhanced by the interface charges,and the breakdown voltage Vbreakdown is increased.EI2=515 V/μm is obtained in the T-DBL SOI SJ.The Vbreakdown of the new device is increased from 124 V of the conventional SOI SJ to 302 V with a 15μm length drift region.The specific on-resistance(Ron,sp)of the T-DBL SOI SJ is only 0.00865Ω?cm2 and the FOM(FOM=V2breakdown/Ron,sp)is 10.54 MW/cm2.
