N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering （DIBL） was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET, These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.
We investigate the negative bias temperature instability （NBTI） of 90nm pMOSFETs under various temperatures and stress gate voltages （Vg）. We also study models of the time （t） ,temperature （T） ,and stress Vg dependence of 90nm pMOSFETs NBTI degradation. The time model and temperature model are similar to previ- ous studies, with small difference in the key coefficients. A power-law model is found to hold for Vg, which is different from the conventional exponential Vg model. The new model is more predictive than the exponential model when taking lower stress Vg into account.
Hot carriers injection （HCI） tests for ultra-short channel n-MOSFET devices were studied. The experimental data of short channel devices （75-90 nm）, which does not fit formal degradation power law well, will bring severe error in lifetime prediction. This phenomenon usually happens under high drain voltage （Vd） stress condition. A new model was presented to fit the degradation curve better. It was observed that the peak of the substrate current under low drain voltage stress cannot be found in ultra-short channel device. Devices with different channel lengths were studied under different Vd stresses in order to understand the relations between peak of substrate current （/sub） and channel length/stress voltage.
