A multi-deposition multi-annealing technique （MDMA） is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device＇s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown （TDDB） characteristics of positive channel metal oxide semiconductor （PMOS） under different MDMA process conditions, including the depo- sition/annealing （D＆A） cycles, the D＆A time, and the total annealing time. The results show that the increases of the number of D＆A cycles （from 1 to 2） and D＆A time （from 15 s to 30 s） can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail （TTF） at 63.2% increases by about several times. However, too many D＆A cycles （such as 4 cycles） make the equivalent oxide thickness （EOT） increase by about 1A and the TTF of PMOS worsen. Moreover, different D＆A times and numbers of D＆A cycles induce different breakdown mechanisms.
The thickness effect of the TiN capping layer on the time dependent dielectric breakdown（TDDB） characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper.Based on experimental results,it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer.From the charge pumping measurement and secondary ion mass spectroscopy（SIMS） analysis,it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density.In addition,the influences of interface and bulk trap density ratio Nit/Not are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo（kMC） method.The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses.
High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to the breakdown characteristic.In this work,a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up,and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation.It is found that all degradation factors,such as trap generation rate time exponent m,Weibull slope β and percolation factor s,each could be expressed as a function of trap density time exponent α.Based on the percolation relation and power law lifetime projection,a temperature related trap generation model is proposed.The validity of this model is confirmed by comparing with experiment results.For other device and material conditions,the percolation relation provides a new way to study the relationship between trap generation and lifetime projection.
A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of n MOSFET during positive bias temperature instability（PBTI） stress based on the recovery measurement. In our case, the extracted energy distribution of negative charges shows an obvious dependence on energy,and the energy level of the largest energy density of negative charges is 0.01 eV above the conduction band of silicon. The charge energy distribution below that energy level shows strong dependence on the stress voltage.
The positive bias temperature instability（PBTI） degradations of high-k/metal gate（HK/MG） n MOSFETs with thin TiN capping layers（1.4 nm and 2.4 nm） are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI（90℃,125℃, 160℃） are studied and activation energy（Ea） values（0.13 eV and 0.15 eV） are extracted. Although the equivalent oxide thickness（EOT） values of two TiN thickness values are almost similar（0.85 nm and 0.87 nm）, the 2.4-nm TiN one（thicker Ti N capping layer） shows better PBTI reliability（13.41% at 0.9 V, 90℃, 1000 s）. This is due to the better interfacial layer/high-k（IL/HK） interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.
： We introduced a TaN/TiAl/top-TiN triple-layer to modulate the effective work function of a TiN-based metal gate stack by varying the TaN thickness and top-TiN technology process. The results show that a thinner TaN and PVD-process top-TiN capping provide smaller effective work function （EWF）, and a thicker TaN and ALD-process top-TiN capping provides a larger EWF; here, the EWF shifts are from 4.25 to 4.56 eV. A physical understanding of the dependence of the EWF on the top-TiN technology process and TaN thickness is proposed. Compared with PVD-TiN room temperature process, the ALD-TiN 400 ℃ process provides more thermal budget. It would also promote more Al atoms to diffuse into the top-TiN rather than the bottom-TiN. Meanwhile, the thicker TaN prevents the Al atoms diffusing into the bottom-TiN. These facts induce the EWF to increase.
Positive bias temperature instability（PBTI） characteristics and degradation mechanisms of NMOSFET with high-k/metal gate last process have been systematically investigated. The time evolution of threshold voltage shift during PBTI stress still follows a power law. However, the exponent n decreases from 0.26 to 0.16 linearly as the gate stress voltage increases from 0.6 to 1.2 V. There is no interface state generation during stress because of the negligible sub-threshold swing change. Moreover, the activation energy is 0.1 e V, which implies that electrons directly tunnel into high-k bulk and are trapped by pre-existing traps resulting into PBTI degradation. During recovery the threshold voltage shift is linear in lgt, and a mathematical model is proposed to express threshold voltage shift.
We evaluated the TiN/TaN/TiA1 triple-layer to modulate the effective work function （EWF） of a metal gate stack for the n-type metal-oxide-semiconductor （NMOS） devices application by varying the TiN/TaN thickness. In this paper, the effective work function of EWF ranges from 4.22 to 4.56 eV with different thicknesses of TiN and TaN. The thinner TiN and/or thinner in situ TaN capping, the closer to conduction band of silicon the EWF is, which is appropriate for 2-D planar NMOS. Mid-gap work function behavior is observed with thicker TiN, thicker in situ TaN capping, indicating a strong potential candidate of metal gate material for replacement gate processed three-dimensional devices such as FIN shaped field effect transistors. The physical understandings of the sensitivity of EWF to TiN and TaN thickness are proposed. The thicker TiN prevents the A1 diffusion then induces the EWF to shift to mid-gap. However, the TaN plays a different role in effective work function tuning from TiN, due to the Ta-O dipoles formed at the interface between the metal gate and the high-k layer.
In the process of high-k films fabrication, a novel multi deposition multi annealing （MDMA） technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing （PDA） times. The equivalent oxide thickness （EOT） decreases when the annealing time（s） change from 1 to 2. Furthermore, the characteristics of SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied systematically. The increase of the PDA time（s） from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.
The characteristics of TDDB （time-dependent dielectric breakdown） and SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied. The EOT （equivalent-oxide-thickness） of the gate stack （Si/SiO2/HfOz/TiN/TiA1/TiN/W） is 0.91 am. The field acceleration factor extracted in TDDB experi- ments is 1.59 s.cm/MV, and the maximum voltage is 1.06 V when the devices operate at 125 ℃ for ten years. A detailed study on the defect generation mechanism induced by SILC is presented to deeply understand the break- down behavior. The trap energy levels can be calculated by the SILC peaks： one S1LC peak is most likely to be caused by the neutral oxygen vacancy in the HfO2 bulk layer at 0.51 eV below the Si conduction band minimum; another SILC peak is induced by the interface traps, which are aligned with the silicon conduction band edge. Fur- thermore, the great difference between the two SILC peaks demonstrates that the degeneration of the high-k layer dominates the breakdown behavior of the extremely thin gate dielectric.
