为解决集成电路的全芯片静电防护设计中寄生电阻导致的防护空间压缩问题,提出了一种实用的能够在版图设计过程中提高集成电路静电放电(ESD)防护能力的仿真方法,用于评估和控制ESD电流通路上的寄生电阻,辅助ESD防护设计,预估器件静电防护等级。详细介绍了仿真方法的原理和流程,以0.18μm SOI CMOS工艺制造的静态随机存储器电路为仿真和实验对象,应用此仿真方法,统计寄生电阻值,优化ESD防护设计,并进行ESD测试,记录未优化样品和优化样品的失效电压。通过对比寄生电阻和失效电压,证明降低寄生电阻可获得更好的ESD防护性能,而且器件失效电压和关键寄生电阻值R Vdd之间存在近似线性反比关系。
This paper presents a new phenomenon,where the holding-voltage of a silicon-controlled rectifier acts as an electrostatic-discharge protection drift in diverse film thicknesses in silicon-on-insulator(SOI) technology. The phenomenon was demonstrated through fabricated chips in 0.18μm SOI technology.The drift of the holding voltage was then simulated,and its mechanism is discussed comprehensively through ISE TCAD simulations.
The performance of a LOCOS-isolated SOI MOSFET heavily depends on its back-gate characteristic, which can be affected by back-gate stress.A large voltage stress was applied to the back gate of SOI devices for at least 30 s at room temperature,which could effectively modify the back-gate threshold voltage of these devices. This modification is stable and time invariant.In order to improve the back-gate threshold voltage,positive substrate bias was applied to NMOS devices and negative substrate bias was applied to PMOS devices.These results suggest that there is a leakage path between source and drain along the silicon island edge,and the application of large backgate bias with the source,drain and gate grounded can strongly affect this leakage path.So we draw the conclusion that the back-gate threshold voltage,which is directly related to the leakage current,can be influenced by back-gate stress.
The human body model(HBM) stress of a no-connect metal cover is tested to obtain the characteristics of abnormal electrostatic discharge,including current waveforms and peak current under varied stress voltage and device failure voltage.A new discharge model called the "sparkover-induced model" is proposed based on the results.Then,failure mechanism analysis and model simulation are performed to prove that the transient peak current caused by a sparkover of low arc impedance will result in the devices’ premature damage when the potential difference between the no-connect metal cover and the chip exceeds the threshold voltage of sparkover.
