为了进一步提高深亚微米SOI(Silicon-On-Insulator)MOSFET(Metal-Oxide Semiconductor Field Effect Transistor)的电流驱动能力,抑制短沟道效应和漏致势垒降低效应,提出了非对称Halo异质栅应变Si SOI MOSFET.在沟道源端一侧引入高掺杂Halo结构,栅极由不同功函数的两种材料组成.考虑新器件结构特点和应变的影响,修正了平带电压和内建电势.为新结构器件建立了全耗尽条件下的表面势和阈值电压二维解析模型.模型详细分析了应变对表面势、表面场强、阈值电压的影响,考虑了金属栅长度及功函数差变化的影响.研究结果表明,提出的新器件结构能进一步提高电流驱动能力,抑制短沟道效应和抑制漏致势垒降低效应,为新器件物理参数设计提供了重要参考.
Based on the exact resultant solution of two-dimensional Poisson＇s equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor （CMOS）-based device in a nanoscale regime.
A clear correspondence between the gated-diode generation-recombination （R-G） current and the performance degradation of an SOI n-channel MOS transistor after F-N stress tests has been demonstrated. Due to the increase of interface traps after F-N stress tests, the R-G current of the gated-diode in the SOI-MOSFET architecture increases while the performance characteristics of the MOSFET transistor such as the saturation drain current and sub-threshold slope are degraded. From a series of experimental measurements of the gated-diode and SOI-MOSFET DC characteristics, a linear decrease of the drain saturation current and increase of the threshold voltage as well as a like-line rise of the sub-threshold swing and a corresponding degradation in the trans-conductance are also observed. These results provide theoretical and experimental evidence for us to use the gated-diode tool to monitor SOI-MOSFET degradation.
This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of short channel effect and draininduced barrier-lowering of CMOS-based devices in nanometre scale.
To reduce the self-heating effect of strained Si grown on relaxed SiGe-on-insulator（SGOI） n-type metal-oxide-semiconductor field-effect transistors（nMOSFETs）,this paper proposes a novel device called double step buried oxide（BOX） SGOI,investigates its electrical and thermal characteristics,and analyzes the effect of self-heating on its electrical parameters.During the simulation of the device,a low field mobility model for strained Si MOSFETs is established and reduced thermal conductivity resulting from phonon boundary scattering is considered.A comparative study of SGOI nMOSFETs with different BOX thicknesses under channel and different channel strains has been performed.By reducing moderately the BOX thickness under the channel,the channel temperature caused by the self-heating effect can be effectively reduced.Moreover,mobility degradation,off state current and a short-channel effect such as drain induced barrier lowering can be well suppressed.Therefore,SGOI MOSFETs with a thinner BOX under the channel can improve the overall performance and long-term reliability efficiently.
Based on the exact resultant solution of two-dimensional Poisson＇s equation in strained Si and Si1-xCex layer, a simple and accurate two-dimensional.analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator （SGOI） MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects （SCE）, the drain-induced barrier-lowering （DIBL） and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.
An electrostatic discharge （ESD） detection circuit with a modified RC network for a 90-nm process clamp circuit is proposed. The leakage current is reduced to 4.6 nA at 25 ℃. Under the ESD event, it injects a 38.7 mA trigger current into the P-substrate to trigger SCR, and SCR can be turned on the discharge of the ESD energy. The capacitor area used is only 4.2 μm2. The simulation result shows that the proposed circuit can save power consumption and layout area when achieving the same trigger efficiency, compared with the previous circuits.
