A fine-grain sleep transistor insertion technique based on our simplified leakage current and delay models is proposed to reduce leakage current. The key idea is to model the leakage current reduction problem as a mixed-integer linear programming （MLP） problem in order to simultaneously place and size the sleep transistors optimally. Because of better circuit slack utilization, our experimental results show that the MLP model can save leakage by 79.75%, 93.56%, and 94.99% when the circuit slowdown is 0%, 3%, and 5%, respectively. The MLP model also achieves on average 74.79% less area penalty compared to the conventional fixed slowdown method when the circuit slowdown is 7%.
This paper presents a novel full-chip scalable routing framework that simultaneously considers the routing congestion and the circuit performance. In order to bridge the gap, the presented framework calls the detailed router immediately after a global route is extracted. With the interleaving mode of global routing immediately followed by detailed routing, accurate routing resource and congestion information can be obtained, which provides valuable guidance for the following global routing process. The framework features the fast pattern and framed shortest path global router,a maze-based congestion-driven detailed router, and better interaction between the two routers. In the framework, timing critical nets can be assigned higher priority for performance concern, and different net ordering techniques can be adopted for different routing objectives. The framework is tested on a set of commonly used benchmark circuits and compared with a previous multilevel routing framework. Experimental results show that the presented framework obtains significantly better routing solutions than the previous one considering circuit performance, routing completion rate, and runtime.
