The cost of the central register file and the size of the program code limit the scalability of very long instruction word(VLIW) processors with increasing numbers of functional units.This paper presents the architectural design of a six-way VLIW digital signal processor(DSP) with clustered register files.The architecture uses a variable length instruction set and supports dynamic instruction dispatching.The one-level memory system architecture of the processor includes 16-KB instruction and data caches and 16-KB instruction and data on-chip RAM.A compiler based on the Open64 was developed for the system.Evaluations show that the processor is suitable for high performance applications with a high code density and small program code size.
A low power digital operational transconductance amplifier(OTA) was developed for low voltage switched capacitor applications.The OTA has a high slew rate(SR) and a large open loop gain with a differential pseudo-two-stage Class-AB structure.A fully compensated depletion mode capacitor is used in the switched capacitor common mode feedback block instead of a metal-insulator-metal(MIM) capacitor to reduce the fabrication cost.Simulations show that with a 1.0-V supply voltage and a 34-pF load at each output terminal,this digital differential pseudo-two-stage Class-AB OTA realized in 0.13-μm technology achieves a 63.5-dB DC gain and a 0.83-V output swing.The slew rate is ±16.29 V/μs and the total power dissipation is only 82 μW.
微系统芯片(System-on-Chip,SoC)发展到今天,集成密度指数增长和芯片面积的急剧膨胀使得全局连线的延时上升,可靠性下降,成为集成电路的设计瓶颈.片上网络(Network-on-Chip,NoC)是解决整个芯片上数据有效传输的结构之一,以片上网络为基础通信架构的微系统芯片称为片上网上系统芯片(System-on-Network-on-Chip,SoNoC).微系统芯片内通信模式兼有随机性和确定性,应该根据特定应用的通信特征设计片上网络.本文在确定SoNoC设计流程的基础上,根据SoNoC的通信特征,选择了合适的离散平面结构,对SoNoC的运算及控制等模块进行布局、对模块间的通信依赖关系进行布线,发展出FRoD(Floor-plan and Routing on Discrete Plane)算法,以自动生成片上网络的拓扑结构.该算法定义了离散平面的一般表示方法,并在四种典型的离散平面上使用不同规模的随机系统完成了系列实验.为了处理系统和网络之间的耦合关系,逐点分裂的布局算法可以逐步学习和适应系统的通信需求,同时优化系统的执行时间和通信能量,在运行随机任务流图的模拟系统上与随机布局结果相比可以节省30%左右的通信能量,20%左右的系统通信时间.串行、并行和串并混合的布线算法使用最短路径把通信关系分布在离散平面的通道上,使不同的通信关系尽量复用网络通道,与全连接网络相比可以节省10%到30%的面积代价.
为了有效地减少分簇VLIW(very long instructionword)处理器结构中簇间数据传输带来的处理器IPC(instructions per-cycle,每周期指令数)的损失,提出了一种新的二维力量引导簇调度算法。该算法采用二维力量引导的方式,在进行簇分配的同时兼顾指令在各个周期上的调度,使指令在各个簇上的均衡分配,有效地产生更小的调度长度。时间复杂度方面,该算法仅为O(n2),优于PCC、模拟退火等循环提高算法;算法性能方面,实现结果表明,利用该算法对分簇VLIW结构进行簇调度,可获得比UAS(unifiedassignment and scheduling)算法更佳的处理器性能。
