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国家高技术研究发展计划(2002AA1Z1580)

作品数:5 被引量:2H指数:1
相关作者:钱鹤李俊峰杨荣韩郑生柴淑敏更多>>
相关机构:中国科学院微电子研究所更多>>
发文基金:国家高技术研究发展计划国家自然科学基金更多>>
相关领域:电子电信更多>>

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改善硅基螺旋电感品质因数的厚铝膜干法刻蚀被引量:1
2006年
提出了一种用于改善硅基螺旋电感品质因数的厚铝膜干法刻蚀技术;这种技术利用氧化硅和光刻胶双层复合掩模来掩蔽厚铝的干法刻蚀,完全兼容于CMOS工艺;应用于双层铝布线,实现了最大厚度达到6μm的顶层铝,显著地减小了螺旋电感的串联电阻,提高了品质因数;该技术同高阻SOI衬底技术相结合,制造的10nH螺旋电感的最大品质因数达到8.6。
杨荣李俊峰钱鹤
关键词:螺旋电感品质因数刻蚀
0.25μm SOI RF nMOSFETs Depleted Partially
2004年
Device structure and fabrication process of SOI nMOSFET depleted partially are p roposed for multi-gigahertz RF applications.Many advanced techniques for deep submiron MOSFETs are incorporated into the proposed device.Main steps and condit ions in process are given in details,with simulation and optimization by using t he process simulator,Tsuprem4.Experiment results of 0.25μm SOI RF nMOSFET are i n consistence with simulated ones,and excellent or acceptable parameters of devi ce performance are obtained for multi-gigahertz RF applications.
李俊峰杨荣赵玉印柴淑敏刘明徐秋霞钱鹤
关键词:STRUCTUREPROCESSEXPERIMENT
A High Performance 0.18μm RF nMOSFET with 53GHz Cutoff Frequency
2006年
This paper presents the fabrication and performance of a 0.18μm nMOSFET for RF applications. This device features a nitrided oxide/poly-silicon gate stack, a lightly-doped-drain source/drain extension, a retrograde channel doping profile, and a multiple-finger-gate layout,each of which is achieved with conventional semiconductor fabrication facilities. The 0.18μm gate length is obtained by e-beam direct-writing. The device is fabricated with a simple process flow and exhibits excellent DC and RF performance: the threshold voltage of 0.52V, the sub-threshold swing of 80mV/dec, the drain-induced-barrier-lowering factor of 69mV/V, the off-state current of 0.5nA/μm, the saturation drive current of 458μA/μm (for the 6nm gate oxide and the 3V supply voltage), the saturation transconductance of 212μS/μm,and the cutoff frequency of 53GHz.
杨荣李俊峰徐秋霞海潮和韩郑生钱鹤
关键词:STRUCTUREPROCESSNMOSFET
一种新的SOI射频集成电路结构与工艺被引量:1
2004年
 立足于与常规CMOS兼容的SOI工艺,提出了电子束/I线混合光刻制造SOI射频集成电路的集成结构和工艺方案。该方案只使用9块掩模版即完成了LDMOS、NMOS、电感、电容和电阻等元件的集成。经过对LDMOS、NMOS的工艺、器件的数值模拟和体硅衬底电感的初步实验,获得了良好的有源和无源器件特性,证明这一简洁的集成工艺方案是可行的。
杨荣李俊峰钱鹤韩郑生
关键词:SOI工艺射频集成电路LDMOSNMOS掩模版硅衬底
A Novel Local-Dielectric-Thickening Technique for Performance Improvements of Spiral Inductors on Si Substrates被引量:1
2005年
A novel local-dielectric-thickening technique i s presented for performance improvements of Si-based spiral inductors.This technique employs the processes of deposition,photolithography,and wet-etching,to locally thicken the oxide layer under the inductor,which can decrease the substrate loss and improve the inductor performance.Both the structures and processes are compact,economical,and compatible with CMOS processing.Several square spiral inductors with different inductances are fabricated,and the quality factors and the self-resonant frequencies both increase clearly with this proposed technique:for the 10nH,5nH,and 2nH inductors,the peak quality factors are effectively improved by 46.7%,49.7%,and 68.6%,respectively;however,the improvement percents of the self-resonant frequencies are more significant,which are 92.1%,91.0%,and no less than 68.1% respectively.
杨荣李俊峰赵玉印柴淑敏韩郑生钱鹤
关键词:SILICONINDUCTOR
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