An improved rate distortion optimization (RDO) a lgorithm in JPEG2000 is proposed. The proposed algorithm is suitable for integra ted circuit (IC) implementation and can reduce 30% computational cost. A hardwar e architecture which includes control unit, memory, divider, data convert er is also given to implement the algorithm. The circuit based on the improved a lgorithm is tested on FPGAs and integrated in a JPG2000 chip codec core.
Xie Xiang Li Cruolin Zhang Chun Zhang Li Wang Zhihua
