In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.
A novel front-end circuit designed for PMT signals processing considering the solution of "Time Walk" correction is discussed in this paper. We are trying to apply the TOT (Time over Threshold) technique to our research. Different from traditional ways, where amplitude is measured, time width is measured for slew correction here, which takes the advantage of TDC. Expensive fast ADCs are abandoned and the whole time measurement electronics design becomes more effective and economical. Test boards have been developed and a convenient method is introduced to evaluate our TOT technique. Results have shown that a 10ps slew correction resolution is achieved throughout the amplitude range from -108mV to -2000mV for negative signals of both 5 ns leading and trailing edge with 10 ns 50%-50% pulse width.
