In this paper, a complementary metal-oxide semiconductor （CMOS）-compatible silicon substrate optimization technique is proposed to achieve effective isolation. The selective growth of porous silicon is used to effectively suppress the substrate crosstalk. The isolation structures are fabricated in standard CMOS process and then this post-CMOS substrate optimization technique is carried out to greatly improve the performances of crosstalk isolation. Three-dimensional electro-magnetic simulation is implemented to verify the obvious effect of our substrate optimization technique. The morphologies and growth condition of porous silicon fabricated have been investigated in detail. Furthermore, a thick selectively grown porous silicon （SGPS） trench for crosstalk isolation has been formed and about 20dB improvement in substrate isolation is achieved. These results demonstrate that our post-CMOS SGPS technique is very promising for RF IC applications.
The via interconnects are key components in ultra-large scale integrated circuits （ULSI）. This paper deals with a new method to create single-walled carbon nanotubes （SWNTs） via interconnects using alternating dielectrophoresis （DEP）. Carbon nanotubes are vertically assembled in the microscale via-holes successfully at room temperature under ambient condition. The electrical evaluation of the SWNT vias reveals that our DEP assembly technique is highly reliable and the success rate of assembly can be as high as 90%. We also propose and test possible approaches to reducing the contact resistance between CNT vias and metal electrodes.
