Electron trapping properties at the HfO2/SiO2 interface have been measured through Kelvin Probe force microscopy,between room temperature and 90 ℃.The electron diffusion in HfO2 shows a multiple-step process.After injection,electrons diffuse quickly toward the HfO2/SiO2 interface and then diffuse laterally near the interface in two sub-steps：The first is a fast diffusion through shallow trap centers and the second is a slow diffusion through deep trap centers.Evolution of contact potential difference profile in the fast lateral diffusion sub-step was simulated by solving a diffusion equation with a term describing the charge loss.In this way,the diffusion coefficient and the average life time at different temperatures were extracted.A value of 0.57 eV was calculated for the activation energy of the shallow trap centers in HfO2.
With the merits of a simple process and a short fabrication period, the capacitor structure provides a convenient way to evaluate memory characteristics of charge trap memory devices. However, the slow minority carrier generation in a capacitor often makes an underestimation of the program/erase speed. In this paper, illumination around a memory capacitor is proposed to enhance the generation of minority carriers so that an accurate measurement of the program/erase speed can be achieved. From the dependence of the inversion capacitance on frequency, a time constant is extracted to quantitatively characterize the formation of the inversion layer. Experimental results show that under a high enough illumination, this time constant is greatly reduced and the measured minority carrier-related program/erase speed is in agreement with the reported value in a transistor structure.
By performing the electronic structure computation of a Si atom, we compare two iteration algorithms of Broyden electron density mixing in the literature. One was proposed by Johnson and implemented in the well-known VASP code.The other was given by Eyert. We solve the Kohn-Sham equation by using a conventional outward/inward integration of the differential equation and then connect two parts of solutions at the classical turning points, which is different from the method of the matrix eigenvalue solution as used in the VASP code. Compared to Johnson＇s algorithm, the one proposed by Eyert needs fewer total iteration numbers.
In this paper the endurance characteristics and trap generation are investigated to study the effects of different postdeposition anneals （PDAs） on the integrity of an Al2O3/Si3N4/SiOz/Si memory gate stack. The flat-band voltage （Vfb） turnarounds are observed in both the programmed and erased states of the N2-PDA device. In contrast, this turnaround is observed only in the erased state of the O2-PDA device. The Vfb in the programmed state of the O2-PDA device keeps increasing with increasing program/erase （P/E） cycles. Through the analyses of endurance characteristics and the low voltage round-trip current transients, it is concluded that in both kinds of device there are an unknown type of pre-existing characteristic deep traps and P/E stress-induced positive oxide charges. In the O2-PDA device two extra types of trap are also found： the pre-existing border traps and the P/E stress-induced negative traps. Based on these four types of defects we can explain the endurance characteristics of two kinds of device. The switching property of pre-existing characteristic deep traps is also discussed.
