Phase change random access memory （PCRAM） is one of the best candidates for next generation non- volatile memory, and phase change SiESbETe5 material is expected to be a promising material for PCRAM. In the fabrication of phase change random access memories, the etching process is a critical step. In this paper, the etching characteristics of Si2Sb2Te5 films were studied with a CF4/Ar gas mixture using a reactive ion etching system. We observed a monotonic decrease in etch rate with decreasing CF4 concentration, meanwhile, Ar concentration went up and smoother etched surfaces were obtained. It proves that CF4 determines the etch rate while Ar plays an im- portant role in defining the smoothness of the etched surface and sidewall edge acuity. Compared with GeESbETe5, it is found that Si2Sb2Te5 has a greater etch rate. Etching characteristics of Si2SbETe5 as a function of power and pressure were also studied. The smoothest surfaces and most vertical sidewalls were achieved using a CF4/Ar gas mixture ratio of 10/40, a background pressure of 40 mTorr, and power of 200 W.
A fully integrated low-jitter, precise frequency CMOS phase-locked loop （PLL） clock for the phase change memory （PCM） drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detector （PFD） with high frequency acquisition, a novel low jitter charge pump, a CMOS ring oscillator based voltage-controlled oscillator （VCO）, a 2nd order passive loop filter, and a digital frequency divider. The design is fabricated in 0.35 #m CMOS technology and consumes 20 mW from a supply voltage of 5 V. In terms of the PCM＇s program operation requirement, the output frequency range is from 1 to 140 MHz. For the 140 MHz output frequency, the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.
The endurance characteristics of phase change memory are studied. With operational cycles, the resis- tances of reset and set states gradually change to the opposite direction. What is more, the operational conditions that are needed are also discussed. The thilure and the changes are concerned with the compositional change of the phase change material. An abnormal phenomenon that the threshold voltage decreases slightly at first and then increases is observed, which is due to the coaction of interthce contact and growing active volume size changing.
In this paper, chemical mechanical planarization （CMP） of amorphous Ge2Sb2Te5 （a-GST） in acidic H2O2 slurry is investigated. It was found that the removal rate of a-GST is strongly dependent on H2O2 concentration and gradually increases with the increase in H2O2 concentration, but the static etch rate first increases and then slowly decreases with the increase in H2O2 concentration. To understand the chemical reaction behavior of H2O2 on the a-GST surface, the potentiodynamic polarization curve, surface morphology and cross-section of a-GST immersed in acidic slurry are measured and the results reveal that a-GST exhibits a from active to passive behavior for from low to high concentration of H2O2. Finally, a possible removal mechanism of a-GST in different concentrations of H2O2 in the acidic slurry is described.
A novel DOIND logic approach is proposed for domino logic, which reduces the leakage current with a minimum delay penalty. Simulation is performed at 70 nm technology node with supply voltage 1V for domino logic and DOIND logic based AND, OR, XOR and Half Adder circuits using the tanner EDA tool. Simulation results show that the proposed DOIND approach decreases the average leakage current by 68.83%, 66.6%, 77.86% and 74.34% for 2 input AND, OR, XOR and Half Adder respectively. The proposed approach also has 47.76% improvement in PDAP for the buffer circuit as compared to domino logic.
In the fabrication of phase change random access memory （PRAM） devices, high temperature thermal processes are inevitable. We investigate the thermal stability of GezSb2Te5 （GST） which is a prototypical phase change material. After high temperature process, voids of phase change material exist at the interface between Ge2Sb2Te5 and substrate in the initial open memory cell. This lower region of GezSb2Te5 is found to be a Te-rich phase change layer. Phase change memory devices are fabricated in different process conditions and examined by scanning electron microscopy and energy dispersive X-ray. It is found that hot-chuck process, nitrogen-doping process, and lower temperature inter-metal dielectric （IMD） deposition process can ease the thermal impact of line-GST PRAM cell.
In this letter, a phase change random access memory(PCRAM) chip based on Ti0.4Sb2Te3 alloy material was fabricated in a 40-nm 4-metal level complementary metal-oxide semiconductor(CMOS) technology. The phase change resistor was then integrated after CMOS logic fabrication. The PCRAM was successfully embedded without changing any logic device and process, in which 1.1 V negative-channel metal-oxide semiconductor device was used as the memory cell selector. The currents and the time of SET and RESET operations were found to be 0.2 and 0.5 m A, 100 and 10 ns,respectively. The high speed performance of this chip may highlight the design advantages in many embedded applications.
In the paper, chemical mechanical planarization （CMP） of Ge2 Sb2Te5 （GST） is investigated using IC 1010 and Politex reg pads in acidic slurry. For the CMP with blank wafer, it is found that the removal rate （RR） of GST increases with the increase of pressure for both pads, but the RR of GST polished using IC 1010 is far more than that of Politex reg. To check the surface defects, GST film is observed with an optical microscope （OM） and scanning electron microscope （SEM）. For the CMP with Politex reg, many spots are observed on the surface of the blank wafer with OM, but no obvious spots are observed with SEM. With regard to the patterned wafer, a few stains are observed on the GST cell, but many residues are found on other area with OM. However, from SEM results, a few residues are observed on the GST cell, more dielectric loss is revealed about the trench structure. For the CMP with IC1010, the surface of the polished blank wafer suffers serious scratches found with both OM and SEM, which may result from a low hardness of GST, compared with those of IC1010 and abrasives. With regard to the patterned wafer, it can achieve a clean surface and almost no scratches are observed with OM, which may result from the high-hardness SiO2 film on the surface, not from the soft GST film across the whole wafer. From the SEM results, a clean interface and no residues are observed on the GST surface, and less dielectric loss is revealed. Compared with Politex reg, the patterned wafer can achieve a good performance after CMP using IC1010.
