A broadband 47–67 GHz low noise amplifier(LNA) with 17.3 d B gain in 65-nm CMOS technology is proposed.The features of millimeter wave circuits are illustrated first and design methodologies are discussed.The wideband input matching of the LNA was achieved by source inductive degeneration,which is narrowband in the low-GHz range but wideband at millimeter-wave frequencies due to the existence of gate–drain capacitance,C gd.In order to minimize the noise figure(NF),the LNA used a common-source(CS) structure rather than cascode in the first stage,and the noise matching principle is explored.The last two stages of the LNA used a cascode structure to increase the power gain.Analysis of the gain boost effect of the gate inductor at the common-gate(CG) transistor is also performed.T-shape matching networks between stages are intended to enlarge the bandwidth.All on-chip inductors and transmission lines are modeled and simulated with a 3-dimensional electromagnetic(EM) simulation tool to guarantee the success of the design.Measurement results show that the LNA achieves a maximum gain of17.3 d B at 60 GHz,while the 3-d B bandwidth is 20 GHz(47–67 GHz),including the interested band of 59–64 GHz,and the minimum noise figure is 4.9 d B at 62 GHz.The LNA absorbs a current of 19 m A from a 1.2 V supply and the chip occupies an area of 900550 m2 including pads.
A wideband low-phase-noise LC voltage-controlled oscillator(VCO) with low VCO gain(KVCO/ variation for WLAN fractional-N frequency synthesizer application is proposed and designed on a 0.13-m CMOS process. In order to achieve a low KVCO variation, an extra switched varactor array was added to the LC tank with the conventional switched capacitor array. Based on the proposed switched varactor array compensation technique,the measured KVCO is 43 MHz/V with only 6.29% variation across the entire tuning range. The proposed VCO provides a tuning range of 23.7% from 3.01 to 3.82 GHz, while consuming 9 mA of quiescent current from a 2.3 V supply. The VCO shows a low phase noise of –121.94 dBc/Hz at 1 MHz offset, from the 3.6 GHz carrier.
A fully integrated 60-GHz transceiver for 802.11ad applications with superior performance in a 90-nm CMOS process versus prior arts is proposed and real based on a field-circuit co-design methodology.The reported transceiver monolithically integrates a receiver,transmitter,PLL(Phase-Locked Loop)synthesizer,and LO(Local Oscillator)path based on a sliding-IF architecture.The transceiver supports up to a 16QAM modulation scheme and a data rate of 6 Gbit/s per channel,with an EVM(Error Vector Magnitude)of lower than−20 dB.The receiver path achieves a configurable conversion gain of 36~64 dB and a noise figure of 7.1 dB over 57~64 GHz,while consuming only 177 mW of power.The transmitter achieves a conversion gain of roughly 26 dB,with an output P1dB of 8 dBm and a saturated output power of over 10 dBm,consuming 252 mW of power from a 1.2-V supply.The LO path is composed of a 24-GHz PLL,doubler,and a divider chain,as well as an LO distribution network.In closed-loop operation mode,the PLL exhibits an integrated phase error of 3.3ºrms(from 100 kHz to 100 MHz)over prescribed frequency bands,and a total power dissipation of only 26 mW.All measured results are rigorously loyal to the simulation.
Coplanar waveguides(CPW) are widely used in mm-wave circuits designs for their good performance.A novel unified model of various on chip CPWs for mm-wave application,together with corresponding direct parameter extraction methodologies,are proposed and investigated,where standard CPW,grounded CPW(GCPW) and CPW with slotted shield(SCPW) are included.Several kinds of influences of different structures are analyzed and considered into the model to explain the frequency-dependent per-unit-length L,C,R,and G parameters,among which the electromagnetic coupling for CPWs with large lower ground or shield is described by a new C–L–R series path in the parallel branch.The direct extraction procedures are established,which can ensure both accuracy and simplicity compared with other reported methods.Different CPWs are fabricated and measured on 90-nm CMOS processes with Short-Open-Load-Through(SOLT) de-embedding techniques.Excellent agreement between the model and the measured data for different CPWs is achieved up to 67 GHz.
