结合Si基n^+-p-n-n^+外延平面双极晶体管,考虑了器件自热、高电场下的载流子迁移率退化和载流子雪崩产生效应,建立了其在高功率微波(high power microwave,HPM)作用下的二维电热模型.通过分析器件内部电场强度、电流密度和温度分布随信号作用时间的变化,研究了频率为1 GHz的等效电压信号由基极和集电极注入时双极晶体管的损伤效应和机理.结果表明集电极注入时器件升温发生在信号的负半周,在正半周时器件峰值温度略有下降,与集电极注入相比基极注入更容易使器件毁伤,其易损部位是B-E结.对初相分别为0和π的两个高幅值信号的损伤研究结果表明,初相为π的信号更容易损伤器件,而发射极串联电阻可以有效的提高器件的抗微波损伤能力.
The instantaneous reversible soft logic upset induced by the electromagnetic interference(EMI) severely affects the performances and reliabilities of complementary metal–oxide–semiconductor(CMOS) inverters. This kind of soft logic upset is investigated in theory and simulation. Physics-based analysis is performed, and the result shows that the upset is caused by the non-equilibrium carrier accumulation in channels, which can ultimately lead to an abnormal turn-on of specific metal–oxide–semiconductor field-effect transistor(MOSFET) in CMOS inverter. Then a soft logic upset simulation model is introduced. Using this model, analysis of upset characteristic reveals an increasing susceptibility under higher injection powers, which accords well with experimental results, and the influences of EMI frequency and device size are studied respectively using the same model. The research indicates that in a range from L waveband to C waveband, lower interference frequency and smaller device size are more likely to be affected by the soft logic upset.
The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave(HPM) is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS inverters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P D AT . Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.
Repeater optimization is the key for SOC(System on Chip) interconnect delay design.This paper proposes a novel optimal model for minimizing power and area overhead of repeaters while meeting the target performance of on-chip interconnect lines.It also presents Lagrangian function to find the number of repeaters and their sizes required for minimizing area and power overhead with target delay constraint.Based on the 65 nanometre CMOS technology,the computed results of the intermediate and global lines show that the proposed model can significantly reduce area and power of interconnected lines,and the better performance will be achieved with the longer line.The results compared with the reference paper demonstrate the validity of this model.It can be integrated into repeater design methodology and CAD(computer aided design) tool for interconnect planning in nanometre SOC.
In the present paper we conduct a theoretical study of the thermal accumulation effect of a typical bipolar transistor caused by high power pulsed microwaves(HPMs),and investigate the thermal accumulation effect as a function of pulse repetition frequency(PRF) and duty cycle.A study of the damage mechanism of the device is carried out from the variation analysis of the distribution of the electric field and the current density.The result shows that the accumulation temperature increases with PRF increasing and the threshold for the transistor is about 2 kHz.The response of the peak temperature induced by the injected single pulses indicates that the falling time is much longer than the rising time.Adopting the fitting method,the relationship between the peak temperature and the time during the rising edge and that between the peak temperature and the time during the falling edge are obtained.Moreover,the accumulation temperature decreases with duty cycle increasing for a certain mean power.
The motion of current filaments in avalanching PIN diodes has been investigated in this paper by 2D transient numerical simulations.The simulation results show that the filament can move along the length of the PIN diode back and forth when the self-heating effect is considered.The voltage waveform varies periodically due to the motion of the filament.The filament motion is driven by the temperature gradient in the filament due to the negative temperature dependence of the impact ionization rates.Contrary to the traditional understanding that current filamentation is a potential cause of thermal destruction,it is shown in this paper that the thermally-driven motion of current filaments leads to the homogenization of temperature in the diode and is expected to have a positive influence on the failure threshold of the PIN diode.
A 10-bit 2.5 MS/s SAR A/D converter is presented.In the circuit design,an R-C hybrid architecture D/A converter,pseudo-differential comparison architecture and low power voltage level shifters are utilized.Design challenges and considerations are also discussed.In the layout design,each unit resistor is sided by dummies for good matching performance,and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error.This proposed converter is implemented based on 90 nm CMOS logic process.With a 3.3 V analog supply and a 1.0 V digital supply,the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively.With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate,the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively,and the power dissipation is measured to be 6.62 mW including the output drivers.This SAR A/D converter occupies an area of 238×214μm^2.The design results of this converter show that it is suitable for multi-supply embedded SoC applications.
This paper presents a theoretical study of the pulse-width effects on the damage process of a typical bipolar transistor caused by high power microwaves(HPMs) through the injection approach.The dependences of the microwave damage power,P,and the absorbed energy,E,required to cause the device failure on the pulse width τ are obtained in the nanosecond region by utilizing the curve fitting method.A comparison of the microwave pulse damage data and the existing dc pulse damage data for the same transistor is carried out.By means of a two-dimensional simulator,ISE-TCAD,the internal damage processes of the device caused by microwave voltage signals and dc pulse voltage signals are analyzed comparatively.The simulation results suggest that the temperature-rising positions of the device induced by the microwaves in the negative and positive half periods are different,while only one hot spot exists under the injection of dc pulses.The results demonstrate that the microwave damage power threshold and the absorbed energy must exceed the dc pulse power threshold and the absorbed energy,respectively.The dc pulse damage data may be useful as a lower bound for microwave pulse damage data.
