A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18μm CMOS process is introduced.By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time,the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased,compared with traditional prescalers.Measurement results show that this synthesizer achieves an in-band phase noise of-87 dBc/Hz at 15 kHz offset,with spurs less than-65 dBc.The whole synthesizer consumes 6 mA in the case of a 1.8 V supply,and its core area is 0.6 mm^2.
The design of a digitally-tunable sixth-order reconfigurable OTA-C filter in a 0.18-μm RFCMOS process is proposed.The filter can be configured as a complex band pass filter or two real low pass filters.An improved digital automatic frequency tuning scheme based on the voltage controlled oscillator technique is adopted to compensate for process variations.An extended tuning range(above 8:1) is obtained by using widely continuously tunable transconductors based on digital techniques.In the complex band pass mode,the bandwidth can be tuned from 3 to 24 MHz and the center frequency from 3 to 16 MHz.
