Methods for improving the high current performance of static induction transistor （SIT） are presented.Many important factors,such as ＂trans-conductance per unit channel width＂ θ, ＂gate efficiency＂ η, ＂sensitivity factor＂ D,and ＂intrinsic static gain＂ μ0,that may be used to describe different aspects of the electrical performance of an SIT are first defined.The dependences of electrical parameters on the structure and technological process of an SIT are revealed for the first time.The packaging technologies are so important for the improvement of high power performance of SITs that they must be paid attention.Testing techniques and circuits for measuring frequency and power parameters of SITs are designed and constructed.The influence of packaging processes in technological practice on the electrical performance of SITs is also discussed in depth.
为了提高功率肖特基整流管的反向击穿电压、抗浪涌能力,采取加场限环的方法从有源区参数、外延材料、流片工艺、产品电参数、可靠性等方面进行全面设计,制造了一种新型结势垒肖特基整流管JBS(Junction Barrier Schottky Rectifier)。经测试,器件的电参数水平正向电压VF为0.85 V^0.856 V,反向电流IR为4.0μA^50.5μA,反向电压VR为307.5 V^465.2 V,抗静电水平从低温退火的6 k V^12 k V提高到15 k V。经高温直流老化测试,器件的可靠性达到了预期的设计要求。
The designing approaches and key fabricating technologies for high frequency high power double dielectrics gate static induction transistor (DDG SIT) with mixed non-saturating I-V characteristics are presented.The effects of parasitic gate-source capacitance (C gs) on the power performance of SIT are discussed.The main methods and considerations to diminish C gs,consequently to improve the high power performance are given.Synchronous epitaxy technology is the critical step to decrease C gs.The 7-μm pitch DDG SIT delivering output power >20W with >7dB power gain and >70% drain efficiency at 400MHz,and delivering output power >7W with >5dB power gain and >50% drain efficiency at 700MHz are successfully fabricated.
