A novel energy recovery logic style ERCCL （energy recovery capacitance coupling logic） , which has good energy performance compared to the conventional CMOS logic and other advanced energy recovery logic, is proposed. ERCCL uses capacitance coupling to perform a logic function, so it can energy-efficiently implement a high fan-in complex logic in a single gate. ERCCL is also a type of threshold logic. The gate count of a system based on ERCCL can be significantly reduced,which,in turn,will decrease the energy loss. A threshold logic synthesis methodology for ERCCL is also presented. MCNC benchmarks are run through the proposed synthesis methodology. The results indicate that about an 80% reduction in gate count can be obtained when compared with the synthesis results of SIS.
Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also proposed,which can adjust duty cycle of MOS switch in power clock generator depending on logic complexity and operating frequency to achieve optimum energy efficiency.Closed-form results are derived,which facilitate efficiency-optimized design of the power clock generator.An ERTL PLA and a conventional PLA are designed and simulated on 0.35μm process.The energy efficiency of the proposed power clock generator can reach 77%～85% operating between 20～100MHz.Simulation results indicate that ERTL is a low energy logic.Including power loss of power clock circuits,ERTL PLA still shows 65%～77% power savings compared to conventional PLA.
