In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor(MOSFET) are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson's equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson's equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.
Current transport mechanism in Ni-germanide/n-type Ge Schottky diodes is investigated using current-voltage characterisation technique with annealing temperatures from 300 C to 500 C.Based on the current transport model,a simple method to extract parameters of the NiGe/Ge diode is presented by using the I-V characteristics.Parameters of NiGe/n-type Ge Schottky diodes fabricated for testing in this paper are as follows:the ideality factor n,the series resistance Rs,the zero-field barrier height b0,the interface state density Dit,and the interfacial layer capacitance Ci.It is found that the ideality factor n of the diode increases with the increase of annealing temperature.As the temperature increases,the interface defects from the sputtering damage and the penetration of metallic states into the Ge energy gap are passivated,thus improving the junction quality.However,the undesirable crystallisations of Ni-germanide are observed together with NiGe at a temperature higher than 400 C.Depositing a very thin(～1 nm) heavily Ge-doped n+ Ge intermediate layer can improve the NiGe film morphology significantly.
We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson's equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.
The fringing-induced barrier lowering(FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain(LDD) overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.
The linear cofactor difference operator(LCDO) method,a direct parameter extraction method for general diodes,is presented.With the developed LCDO method,the extreme spectral characteristic of the diode voltage-current curves is revealed,and its extreme positions are related to the diode characteristic parameters directly.The method is applied to diodes with different sizes and temperatures,and the related characteristic parameters,such as reverse saturation current,series resistance and non-ideality factor,are extracted directly.The extraction result shows good agreement with the experimental data.
