A physical model of hole mobility for germanium-on-insulator p MOSFETs is built by analyzing all kinds of scattering mechanisms, and a good agreement of the simulated results with the experimental data is achieved, confirming the validity of this model. The scattering mechanisms involved in this model include acoustic phonon scattering, ionized impurity scattering, surface roughness scattering, coulomb scattering and the scattering caused by Ge film thickness fluctuation. The simulated results show that the coulomb scattering from the interface charges is responsible for the hole mobility degradation in the low-field regime and the surface roughness scattering limits the hole mobility in the high-field regime. In addition, the effects of some factors, e.g. temperature, doping concentration of the channel and the thickness of Ge film, on degradation of the mobility are also discussed using the model, thus obtaining a reasonable range of the relevant parameters.
A GaAs metal-oxide-semiconductor （MOS） capacitor with HfO2 as gate dielectric and silicon nitride （SiNx） as the interlayer （IL） is fabricated. Experimental results show that the sample with the SiNx IL has an improved capacitance- voltage characteristic, lower leakage current density （0.785 × 10^-6 Alcm^2 at Vfo ＋ 1 V） and lower interface-state density （2.9 × 10^12 eV^-1 ·cm^-2） compared with other samples with N2- or NH3-plasma pretreatment. The influences of post- deposition annealing temperature on electrical properties are also investigated for the samples with SiNx IL. The sample annealed at 600 ℃ exhibits better electrical properties than that annealed at 500 ℃, which is attributed to the suppression of native oxides, as confirmed by XPS analyses.
A threshold-voltage model for a stacked high-k gate dielectric GaAs MOSFET is established by solving a two-dimensional Poisson＇s equation in channel and considering the short-channel, DIBL and quantum effects. The simulated results are in good agreement with the Silvaco TCAD data, confirming the correctness and validity of the model. Using the model, impacts of structural and physical parameters of the stack high-k gate dielectric on the threshold-voltage shift and the temperature characteristics of the threshold voltage are investigated. The results show that the stacked gate dielectric structure can effectively suppress the fringing-field and DIBL effects and improve the threshold and temperature characteristics, and on the other hand, the influence of temperature on the threshold voltage is overestimated if the quantum effect is ignored.
